The present invention generally relates to a semiconductor integrated circuit, and in particular to a semiconductor integrated circuit constructed by systematically combining a plurality of integrated circuits formed on a wafer, each having a self-testing function.
Recently, wafer-scale semiconductor integrated circuits have been developed and fabricated. A wafer-scale integrated circuit is defined as an integrated circuit formed by the entire wafer or an integrated circuit having similar scale to an integrated circuit using the whole of one wafer. The wafer-scale integrated circuit is large in scale, as compared with conventional chip-scale semiconductor integrated circuit. For example, a wafer of an order of about 3 to 6 inches is used for the wafer-scale integrated circuit. In addition, the wafer-scale integrated circuit has more input/output terminals (300-1000 in general) than the conventional integrated circuits.
The wafer-scale integrated circuit includes a plurality of integrated circuit blocks. An integrated circuit block is defined as an integrated circuit for carrying out logical operations. This means that the intgrated circuit block includes an adder, a multiplier or a multiplier accumulator or an arbitrary combination thereof in digital form. For example, each of the integrated circuit blocks can form a butterfly computation processor. The integrated circuit blocks may be arbitrarily combined with other circuit blocks on the same wafer, so that a logical operating system can be obtained. For example, a four point fast Fourier transform processor may be configured by coupling 4 integrated circuit blocks each having the function of butterfly computation.
As in the case of conventional semiconductor integrated circuits, it is necessary to test the operation of the wafer-scale integrated circuit. An integrated circuit (abbreviated as IC) tester is used for testing the chip-scale semiconductor integrated circuits. The IC tester has probes supported by probe guards for checking operation of the integrated circuit in a waer state where the integrated circuit has not yet been packaged. Upon the operation test, the probes come in contact with pads mounted on the wafer. However, the IC tester is not suitable for testing the wafer-scale integrated circuit because it is difficult to keep pressure against the probes uniform and to precisely position the probes with respect to the corresponding pads. In addition, the currently available IC tester has 256 input/output terminals at maximum.
Also, a board tester is used for printed circuit boards. The currently available board tester has 1024 input/output terminals at maximum. However, since contact with the pads on the board is made by use of edge connectors, the board tester cannot be used for testing the wafer-scale integrated circuit.
From the point of view mentioned above, conventionally, self-testing circuits are built in the wafer-scale integrated circuit. In detail, one integrated circuit block is provided with one self-testing circuit. By the self-testing circuits, each integrated circuit can be tested. It should be noted that testing only each individual integrated circuit block is not enough to check operation of the wafer-scale integrated circuit. This is because some integrated circuit blocks are combined to form a logic system. In other words, in order to check the wafer-scale semiconductor circuit more completely, it is also necessary to test the logical operation system in addition to the individual integrated circuit blocks.
In the conventional wafer-scale integrated circuits, a self-testing circuit for testing the system is added to the systematically constructed integrated circuits. The self-testing circuit for the system test is mounted on the wafer. That is, a particular region of the wafer is necessary for mounting the self-testing circuit. This causes a decrease in the integration density of the wafer-scale semiconductor device.